1. Technical Field
The present invention relates to a sampling rate converting method and circuit for converting data having different rates, which is input to a plurality of synchronous serial circuits of which transmission clock signals (hereinafter, referred to as “clock”) are asynchronous, into a same sampling rate.
2. Description of the Related Art
For example, when two input digital audio (speech) signals having different sampling rates of 48 KHz and 32 KHz in broadcasting satellite are converted into an output digital audio signal having a sampling rate of 44.1 KHz to be recorded in a compact disc (CD), a sampling rate converting circuit for converting the two input digital audio signals (having the sampling rate of 48 KHz and 32 KHz) into one output digital audio signal (having the sampling rate of 44.1 KHz) is needed.
Conventionally, a sampling rate converting method or circuit is disclosed in Japanese Patent Kokai No. 5-327409 (Patent Document 1) and Japanese Patent Kokai No. 8-125493 (Patent Document 2).
In general, in 3-wired serial data communication of a digital audio signal, three signals including a clock clk, a channel signal ch, and data D(Fs) which is a digital audio signal are transmitted. A transmission master circuit (master circuit) outputs timing signals CK (clock clk and channel signal ch) and a reception slave circuit (slave circuit) receives the data D(Fs) and outputs D′(Fs′) in synchronization with the clock clk. To this end, in the sampling rate converting circuit provided in the slave circuit, synchronization is performed by a reference signal (clock clk or input timing signal ck which is the channel signal ch) transmitted from the master circuit, multiply is, if necessary, performed by a phase-locked loop (PLL), and an operation portion is performed depending on the clock clk of the master circuit.
FIG. 1 shows a schematic configuration of a conventional sampling rate converting circuit.
The sampling rate converting circuit includes a serial/parallel converting circuit 1 for converting serial data into parallel data, a finite impulse response (FIR) circuit 10 for performing a FIR filter operation, and a resampling circuit 19.
Among an input timing signal CK1 and input data D1(Fs1) which is a digital audio signal having any sampling frequency Fs1 transmitted from the master circuit, the input data D1(Fs1) is converted into the parallel data by the serial/parallel converting circuit 1 and the parallel data is subjected to a filter process (oversampling) by the FIR circuit 10. The oversampled data is resampled based on an output timing signal CK′ by the resampling circuit 19 and output as output data D1′(Fs′) which is a digital audio signal.
In paragraphs 0014 and 0016 to 0018 and FIG. 1 of Patent Document 1, there is disclosed a technology of performing a FIR operation at points of times t3 and t4 among points of times t1 to t4 obtained by quartering a period of a first clock P21 synchronized with input data which is a digital audio signal before sampling rate conversion, based on a second clock P27 synchronized with output data which is a digital audio signal after the sampling rate conversion and reducing a multiplication coefficient applied to a FIR digital filter, in a FIR digital filter for performing oversampling.
In addition, in claim 1 and paragraphs 0045 and 0046 of Patent Document 2, there is disclosed a technology of applying f2/k multiple oversampling to first sampling data and extracting data from each of f1/k sets of data based on the oversampled result when a prescribed integer k is selected so that f1/k and f2/k are both integers, thereby suppressing signal level error from increasing, obtaining output data with high precision, and simplifying a circuit configuration, in a sampling rate converter that provides an output of an input signal sampled by a first sampling frequency f1 as a signal with a second sampling frequency f2.
However, in the conventional sampling rate converting circuit or method shown in FIG. 1, since the input of the input data D1(Fs1) and the output of the output data D1′(Fs′) should be controlled depending on the master circuit operation clock clk transmitted from the transmission master circuit, the FIR circuit 10 should be operated based on the clock clk. To this end, following problems (A) and (B) are caused.
(A) A case where plural pieces of input data having different sampling frequencies are input
FIG. 2 shows a schematic configuration when mixing plural pieces of input data having different sampling frequencies using the conventional method shown in FIG. 1.
When processing plural pieces (N) of input data having different sampling frequencies [input data D1(Fs1) having a sampling frequency Fs1 (for example, 48 KHz), input data D2(Fs2) having a sampling frequency Fs2 (for example, 32 KHz), . . . , and input data DN having a sampling frequency FsN] transmitted from the slave circuit, N sampling rate converting circuits shown in FIG. 2 are generally required. The N sampling rate converting circuits include serial/parallel converting circuits 1-1, 1-2, . . . , and 1-N for receiving the input data D1(Fs1), D2(Fs2), . . . , and DN(FsN) and input timing signals CK1, CK2, . . . , and CKN, FIR circuits 10-1 to 10-N, and resampling circuits 19-1 to 19-N for outputting output data D1′(Fs′), D2′(Fs′), . . . and DN′(Fs′) based on a common output timing signal CK′.
Since the FIR circuits 10-1 to 10-N provided in the sampling rate converting circuits perform operations on the plural pieces of input data D1(Fs1), D2(Fs2), . . . , and DN(FsN) which are asynchronously input, that is, perform oversampling of the input data D1(Fs1), D2(Fs2), . . . , and DN(FsN) having different sampling frequencies Fs1, Fs2, and FsN, times required for the FIR operations on the input data D1(Fs1), D2(Fs2), . . . , and DN(FsN) are different from one another. To this end, it is difficult to provide a common FIR circuit 10 instead of the plurality of FIR circuits 10-1 to 10-N and to perform the operations on the input data D1(Fs1), D2(Fs2), . . . , and DN(FsN) in a time division fashion. Accordingly, it is difficult to unify (share) the plurality of FIR circuits 10-1 to 10-N to reduce a circuit area.
(B) A case where a magnification ratio of an input frequency and an output frequency is not an integer
FIG. 3 shows an example of a conventional oversampling method in the sampling rate converting circuit shown in FIG. 1. In FIG. 3, for example, a configuration of oversampling a sampling frequency Fs (before conversion) to 2(n+1) times using the FIR circuit 10 shown in FIG. 1 is shown. The FIR circuit 10 for oversampling includes a high-order FIR filter, n low-order FIR filters [or infinite impulse response (IIR) filter]. In the FIR circuit 10, the sampling frequency Fs of input data X1, X2, X3, . . . is oversampled to output data of a sampling frequency (2(n+1))Fs. This data is resampled based on an output timing signal CK′ (sampling frequency Fs′) by the resampling circuit 19 and output data Y1, Y2, . . . are output.
FIG. 4 shows an example of resampling after oversampling using the conventional method shown in FIG. 3. In FIG. 4, abscissa represents a time and ordinate represents an amplitude. In addition, oversampling wavelengths of x2, x4, x8 of the input data X1, X2, X3 and wavelengths of output data Y1 and Y2 are shown.
FIGS. 5A and 5B show a relationship between an input frequency and a FIR position (sampling position), where FIG. 5A shows a case where the output frequency is higher than the input frequency and FIG. 5B shows a case where the output frequency is lower than the input frequency.